Charge-Coupled Device (CCD) image sensors capture images using an array of photosensitive areas that collect charge in response to light. FIG. 1 is a simplified block diagram of a prior art CCD image sensor. Image sensor 100 includes vertical charge-coupled device (VCCD) shift registers 102 that each include a column of charge storage elements 104. For simplicity, only three VCCD shift registers are shown in FIG. 1. When an image is captured by image sensor 100, charge packets 106 in the VCCDs 102 are shifted in parallel one row at a time to charge storage elements 108 in horizontal CCD (HCCD) shift register 110. Each row of charge in HCCD 110 is shifted serially one charge storage element 108 at a time to output circuit 112. Output circuit 112 converts the charge packets into analog voltage output signal (Vout). Other components in an imaging system typically process and redisplay the pixels to reproduce the captured image.
Depending on frame rate requirements, it may be necessary to increase the speed of charge transfer from the image sensor to the rest of the imaging system. Common approaches include increasing the transfer rate of the shift registers or providing additional output structures where each output handles only a portion of the total number of pixels. A commonly found example of a prior art image sensor with multiple output structures is shown in FIG. 2. The gate electrodes (not shown) overlying the array of pixels 200 run continuously across the entire array. The clocking signals applied to the gate electrodes shift charge out of the array and into one of four different output structures 202, 204, 206, 208. This arrangement is sometimes referred to as quadrant readout architecture.
Additionally, an image sensor having the architecture shown in FIG. 2 can be constructed and driven with a flexible clocking scheme such that the pixels are readout of pixel array 200 in arrangements other than the four output quadrant mode. For example, in image sensors such as the commercially available Kodak KAI-01050 CCD image sensor, pixels can be alternatively readout into any one, two or even three output structures. This flexible readout architecture enables a camera designer to trade off frame rate by deciding how many outputs a camera will support. Using fewer outputs generally reduces camera electronics costs, simplifies image reconstruction and improves image quality.
In some situations, it is desirable to improve the sensitivity and signal-to-noise ratio of an image sensor through charge amplification or multiplication. FIG. 3 illustrates a prior art image sensor that includes an extended HCCD shift register for the purpose of amplifying the signal of a captured image. HCCD shift register 300 and charge multiplication HCCD shift register 302 both include charge storage elements that are each driven by one or more gate electrodes (not shown). Charge is shifted from HCCD shift register 300 into charge multiplication shift register 302. Charge multiplication or amplification occurs during charge transfer in charge multiplication shift register 302 through the application of large voltages to the overlying gate electrodes in the shift register 302. The resulting large electric fields within the silicon produce a signal larger than originally detected in the pixels in pixel array 304. Many factors control the amount of signal amplification including the amount of charge present, the extent of the electric field strength and the number of amplifying stages in the charge multiplication shift register 302. U.S. Pat. Nos. 4,912,536, 5,337,340, 6,444,968, 6,784,412, 7,139,023 and 7,420,605 disclose various methods and structures for charge multiplication.
One limitation to charge multiplying HCCD shift register 302 in some image sensors is be the increased die size and associated higher manufacturing costs. In addition, if the number of phases in the charge multiplying HCCD shift register 302 is not an even multiple of HCCD shift register 300, then line and frame rates are degraded as result of having to spend additional time clocking the extra HCCD phases not associated to image data.
U.S. Pat. No. 7,522,205 describes an architecture where the HCCD shift register is operated in normal fashion for full image resolution readout and alternately as a charge multiplication HCCD shift register for half image resolution readout. FIG. 4 depicts the operation of a CCD image sensor during full image resolution readout mode as disclosed in U.S. Pat. No. 7,522,205. FIG. 5 illustrates the operation of the CCD image sensor shown in FIG. 4 during the charge multiplication mode. HCCD shift register 400 can be operated to shift charge to one or two outputs in normal readout (FIG. 4) by means of independent sets of HCCD clocks, HA and HB. During charge multiplication readout mode (FIG. 5), both HA and HB are operated such that charge transfer occurs in only one direction and HA clock voltages are increased to achieve the desired charge multiplication. A split fast dump row structure 500, 502 is used to independently control whether or not charge packets from the left side 504 or the right side 506 of the pixel array are allowed to transfer into HCCD shift register 400. FIG. 5 illustrates bow charge packets in the columns associated with the left side 504 are prevented from dropping down into HCCD shift register 400 by the split fast dump row structure 500 so as to avoid interfering with the charge packets being readout from the previous line on the right side 506 of the pixel array. The charge multiplication mode shown in FIG. 5 can keep the frame rate constant but produces a half resolution image because half of the image is lost or thrown away through the fast dump row structure 500.